This invention generally relates to the testing of Field Programmable Gate Array (FPGA) systems. In particular, the invention relates to testing of inter-device connections among multiple FPGAs on products and development boards that use multiple FPGAs.
The use of FPGAs in various development boards including prototype boards and tester boards is very common. Due to their programmable features, FPGAs offer inexpensive and fast means for testing various integrated circuit designs before building a maskwork for a final product. A typical development board comprises multiple FPGAs interconnected to each other.
The prior art offers limited capabilities for testing development boards comprising multiple FPGAs. One commonly known testing method is termed a xe2x80x9cbed of nailsxe2x80x9d test. Under this test, a development board to be tested is placed on an Automated Testing Equipment (ATE) device such that a plurality of conducting pins of the ATE, i.e., the xe2x80x9cbed of nailsxe2x80x9d, are brought into contact with selected portions or selected terminals of the various devices mounted on the development board.
The ATE applies electrical signals to various selected terminals on the development board, and waits for response signals at the same and/or other terminals. The response signals from these selected terminals are analyzed within the ATE and/or forwarded from the bed of nails terminals to further equipment for analysis. In this manner, the response signals received in response to the input electrical signals applied by the ATE can be compared to the expected output signals. If the development board fails to respond in the expected manner, a defect is indicated.
The bed of nails test is expensive and only verifies the schematic layout of a development board. Under this test, the development board is tested on the initial build, prior to any FPGA components being mounted or soldered. The test does not provide for any testing after FPGAs and other Integrated Circuit (IC) components are mounted or soldered on the board.
One prior art method for testing IC""s after they have been mounted on a development board is JTAG scan. A JTAG scan chain test may be utilized to test a development board on which FPGAs are already mounted. This test checks the I/O (Input/Output) toggle on FPGAs and on other IC components. However, JTAG does not exist on many FPGA devices. Furthermore, for the few that employ actual JTAG, there is an area and cost penalty.
Thus, there exists a need for a flexible testing circuit or testing device which may test not only the board traces but also the associated solder bump bonds, i.e., inter-device connections among multiple FPGAs, while not incurring the area/cost penalties associated with dedicated JTAG circuitry.
The present invention provides a testing device to test inter-device FPGA links among multiple FPGAS. Unlike a dedicated conventional JTAG circuit which tests all the I/O pins, the inventive testing device can be programmed to test a subset of I/O pins required for a specific application. After completing a test for a specific application, the testing device may be configured and reused for another application.
In the preferred embodiment, a testing device comprises a control circuit coupled to a unidirectional shift register. The control circuit comprises a clock generator, a pattern generator, a descrambler, a comparator, and a recorder.
The shift register comprises a plurality of flip-flops and buffers which form a shift block through various inter-device FPGA links to be tested. This shift register is customarily designed for each different type of test by instructional means or other programmable means. This shift register may be configured from the existing elements of FPGAs.
The shift register accepts a pattern signal from the control circuit as an input signal and communicates it over the FPGA inter-device links to be tested. It then generates an output signal back to the control circuit. The control circuit compares the input and output signal to determine whether FPGA links are working according to specification.
In an alternative embodiment, a testing device comprises a control circuit and a bi-directional shift register. In this shift register, pattern signals travel on a route in one direction, and then reverse the direction to travel backwards on the same route. This testing device not only checks whether FPGA links are working properly but also provides feedback on the source of the problem.
In another alternative embodiment, a testing device comprises a plurality of input buffers to receive input control signal, a plurality of flip-flops to communicate these input signals over a plurality of inter-device FPGA links, and a plurality of output buffers to output the control signals. The output control signals are compared to the expected output. If the signal patterns match, the results are pass indicating the operational integrity of inter-device FPGA the links mismatch indicates a fault.
Even though this testing device tests multiple inter-device FPGA links, the output from each FPGA link is received on a particular output buffer. Therefore, the output signal is monitored in real-time, and the problems are also detected in real-time. Also, the fault indication immediately points to the source of the problem.
In the preferred embodiment, the shift register components (e.g. flip-flops and buffers) are formed by the existing components of the FPGA.
The inventive device provides a user with the ability to choose the number of FPGA links to be tested. The testing device also provides a user flexibility to choose the pattern of the input signal to be transmitted through the shift register.